TLM Synthesis Studio
In our proposed system level design flow, a designer can partition a high level system specification into computation and communication parts. In the next step, the designer can model the communication parts by using our powerful TLM library of communication protocols. The computation parts can be modeled in terms of high level C/C++ or SystemC RT level. TLM synthesis uses a library of synthesizable TLM protocols to synthesize transaction level descriptions into SystemC RTL code. The designer can either specify the TLM design in terms of several supported commercial bus structures, or use the standard TLM channels in his or her design to be synthesized. Either way, our tool creates synthesizable RT level SystemC code from the TLM design. Our integrated environment provides paths to pre-synthesis TLM simulation, as well as post-synthesis RTL simulation. Various timed and untimed TLM models are generated for faster TLM simulations.
General Features:
- Library of TLM Synthesizable Components
- Embedded Processors
- Embedded Buses
- On-Chip Memory
- Peripheral Components
- User-Defined Modules
- Environment forMixed-Level Simulation
- Design, Simulation, and Synthesis of SystemC TLM Models
- TLM Syntax Highlighting Editor
- Modeling at Different Levels of Abstraction
- Un-Timed
- Approximate-Timed
- Cycle-Accurate
- Pin-Accurate (RTL)
Contact Info:
- Parisa Razaghi: parisa@cad.ece.ut.ac.ir
