Mixed-Signal Simulator

Mixed-Signal Simulator

Mixed-Signal Simulator is a mixed-signal, mixed-domain and mixed-language design environment which supports VHDL-AMS 1999, VHDL 2002, Verilog 2001, SystemVerilog 2005 assertions and SystemC 2005.

General Features:

• Mixed HDL Simulation
  • VHDL-AMS, Verilog, and SystemC
• Mixed Signal Simulation
  • Analog and Digital Signal Simulation through VHDL-AMS
• Mixed Domain Analog Simulation
  • Electrical, Thermal, and Mechanical
• SystemVerilog-like Assertions Embedded in
  • VHDL-AMS, Verilog, and SystemC

Contact Info:

• Ali Shahabi: shahabi@cad.ece.ut.ac.ir