SystemC Studio
UT SystemC Studio is a SystemC Environment for conversion between VHDL/Verilog and SystemC, SystemC simulation, SystemC assertion-based verification, and testbench generation.
General Features:
- Conversion
- VSC (VHDL/Verilog to SystemC Conversion)
- TVS (SystemC to VHDL/Verilog Conversion)
- SystemC Assertion-based VerificationVHDL, Verilog, and SystemC Editors
- System Level Verification Look like OVL Assertions
- SystemC Simulation
- Waveform Viewer/Editor
- Different Formats: VCD, SystemC WIF, Custom binary format
- Edit Waveform
- Single Value, Clock, Counter, Formula, Random
- Generate Simple Testbench
- VHDL, Verilog, and SystemC
Contact Info:
- Amir Masoud Gharebaghi: amir@cad.ece.ut.ac.ir
