RTL+Introduction رشد روز افزون پیچیدگی طراحی سیستم‌های دیجیتال، توسعه محیط‌هایی با قابلیت توصیف سیستم در سطح بالا را ضروری می‌سازد. چنین محیطی امکان چشم‌پوشی از برخی جزئیات طراحی را برای طراح فراهم ساخته و در نتیجه موجب افزایش سرعت طراحی سیستم و ساده‌سازی این فرآیند می‌گردد. در کنار ساده‌سازی روال طراحی، یکی از مهم‌ترین مسائل […]
TLM Synthesis Studio In our proposed system level design flow, a designer can partition a high level system specification into computation and communication parts. In the next step, the designer can model the communication parts by using our powerful TLM library of communication protocols. The computation parts can be modeled in terms of high level […]
SystemC Studio UT SystemC Studio is a SystemC Environment for conversion between VHDL/Verilog and SystemC, SystemC simulation, SystemC assertion-based verification, and testbench generation. General Features: Conversion VSC (VHDL/Verilog to SystemC Conversion) TVS (SystemC to VHDL/Verilog Conversion) SystemC Assertion-based VerificationVHDL, Verilog, and SystemC Editors System Level Verification Look like OVL Assertions SystemC Simulation Waveform Viewer/Editor Different […]
Mixed-Signal Simulator Mixed-Signal Simulator is a mixed-signal, mixed-domain and mixed-language design environment which supports VHDL-AMS 1999, VHDL 2002, Verilog 2001, SystemVerilog 2005 assertions and SystemC 2005. General Features: Mixed HDL Simulation VHDL-AMS, Verilog, and SystemC Mixed Signal Simulation Analog and Digital Signal Simulation through VHDL-AMS Mixed Domain Analog Simulation Electrical, Thermal, and Mechanical SystemVerilog-like Assertions […]
UT Assertion-based Verification Package UTAVP (University of Tehran TLM Assertion-based Verification Package) is a package to aid system level designers debug and verify their SystemC RTL and TLM designs. This package provides designers with an OVL-equivalent assertion package ported to SystemC, a package of transaction level assertions, and a library of enhanced HDL OVL […]
Test Hardware Evaluation Package This environment gives hardware design and test engineers implementation capabilities like those of expert programmers. We have developed PLI/VPI functions to relieve hardware engineers from getting involved in elaborate software programming and data structure. You don’t need to port your design back and forth through different design and test formats. General […]
ESL Design Methodology A methodology for design of complex digital systems at system level through a training video. After the introduction to SystemC and TLM-2.0, the video explains a number of design sub-levels and guidelines for design at each sub-level. A test data compression system is implemented as a case study using OSCI TLM 2.0 […]
Multi Level Test Package MLT (Multi Level Test Package) is a package for testing system level designs, whose processing elements are described using basic hardware structures implemented in C++, and communications are SystemC TLM channels or interfaces. C++ enhanced gate level processing elements and communication channels are being tested using C++ test applications. General Features: […]
Multi Level Test Package MLT (Multi Level Test Package) is a package for testing system level designs, whose processing elements are described using basic hardware structures implemented in C++, and communications are SystemC TLM channels or interfaces. C++ enhanced gate level processing elements and communication channels are being tested using C++ test applications. General Features: […]
Migrating from RTL to ESL via SystemC This training package is presented for describing hardware with C++ and SystemC. The package contains videos, reading materials, slides, and software. After covering the basics, the RT-level with a section on VHDL is started and followed by a corresponding SystemC presentation, and then moving up into SystemC channels. […]
