UT Assertion-based Verification Package
UTAVP (University of Tehran TLM Assertion-based Verification Package) is a package to aid system level designers debug and verify their SystemC RTL and TLM designs. This package provides designers with an OVL-equivalent assertion package ported to SystemC, a package of transaction level assertions, and a library of enhanced HDL OVL assertions to verify synthesized RTL level TLM channels.
General Features:
- OVL assertion for RTL SysyemC
- Converting Verilog OVL assertions into SystemC
- Verify the functionality of SystemC modules used in a TLM design
- TLM channel assertions
- Creating verifiable channels
- Synthesized TLM channel assertions
- Synthesizing channels into RTL
Contact Info:
- Amir Ali Ghofrani: ghofrani@cad.ece.ut.ac.ir
