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ao68000 top level module.
This module contains only instantiations of sub-modules and wire declarations.
Initiate WISHBONE MASTER bus cycles.
The bus_control module is the only module that has contact with signals from outside of the IP core. It is responsible for initiating WISHBONE MASTER bus cycles. The cycles can be divided into:
Every cycle is supplemented with the following tags:
The bus_control module is also responsible for registering interrupt inputs and initiating the interrupt acknowledge cycle in response to a microcode request. Microcode requests a interrupt acknowledge at the end of instruction processing, when the interrupt privilege level is higher than the current interrupt privilege mask, as specified in the MC68000 User's Manual.
Finally, bus_control controls also two ao68000 specific core outputs:
Microcode controlled registers.
Most of the ao68000 IP core registers are located in this module. At every clock cycle the microcode controls what to save into these registers. Some of the more important registers include:
Contains the microcode ROM and D0-D7, A0-A7 registers.
The memory_registers module contains:
Currently this module contains altsyncram instantiations from Altera Megafunction/LPM library.
Decode instruction and addressing mode.
The decoder is an instruction and addressing mode decoder. For instructions it takes as input the ir register from the registers module. The output of the decoder, in this case, is a microcode address of the first microcode word that performs the instruction.
In case of addressing mode decoding, the output is the address of the first microcode word that performs the operand loading or saving. This address is obtained from the currently selected addressing mode saved in the ea_mod and ea_type registers in the registers module.
Condition tests.
The condition module implements the condition tests of the MC68000. Its inputs are the condition codes and the currently selected test. The output is binary: the test is true or false. The output of the condition module is an input to the microcode_branch module, that decides which microcode word to execute next.
Arithmetic and Logic Unit.
The alu module is responsible for performing all of the arithmetic and logic operations of the ao68000 processor. It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into a result 32-bit register. This register is located in the alu module.
The alu module also contains the status register (SR) with the condition code register. The microcode decides what operation the alu performs.
Select the next microcode word to execute.
The microcode_branch module is responsible for selecting the next microcode word to execute. This decision is based on the value of the current microcode word, the value of the interrupt privilege level, the state of the current bus cycle and other internal signals.
The microcode_branch module implements a simple stack for the microcode addresses. This makes it possible to call subroutines inside the microcode.