Operation

The ao68000 IP Core is designed to operate in a similar way as the original MC68000. The most import differences are:

Setting up the core

The ao68000 IP Core has an WISHBONE MASTER interface. All standard memory access bus cycles conform to the WISHBONE specification. These cycles include:

The cycles are either Single, Block or Read-Modify-Write (for the TAS instruction). When waiting to finish a bus cycle the ao68000 reacts on the following input signals:

There is also a special bus cycle: the interrupt acknowledge cycle. This cycle is a reaction on receiving a external interrupt from the ipl_i inputs. The processor only samples the ipl_i lines after processing an instruction, so the interrupt lines have to be asserted for some time before the core reacts. The interrupt acknowledge cycle is performed in the following way:

The ao68000 reacts on the following signals when waiting to finish a interrupt acknowledge bus cycle:

Every bus cycle is supplemented with output tags:

The ao68000 core has two additional outputs that are used to indicate the state of the processor:

Resetting the core

The ao68000 core is reset with a asynchronous reset_n input. After deasserting the signal, the core starts its standard startup sequence, which is similar to the one performed by the original MC68000:

An identical sequence is performed when powering up the core for the first time.

Processor modes

The ao68000 core has two modes of operation - exactly like the original MC68000:

Performing a privileged instruction when running in user mode results in a privilege exception, just like in MC68000.

Processor states

The ao68000 core can be in one of the following states: