Contains the microcode ROM and D0-D7, A0-A7 registers. More...
Always Constructs | |
ALWAYS_30 | ( clock , reset_n ) |
Inputs | |
clock | |
reset_n | |
An_address | [3:0] |
An_input | [31:0] |
An_write_enable | |
Dn_address | [2:0] |
Dn_input | [31:0] |
Dn_write_enable | |
Dn_size | [2:0] |
micro_pc | [8:0] |
Outputs | |
An_output | [31:0] |
usp | reg[31:0] |
Dn_output | [31:0] |
micro_data | [87:0] |
Module Instances | |
altsyncram::an_ram_inst | |
altsyncram::dn_ram_inst | |
altsyncram::micro_rom_inst | |
Signals | |
wire | An_ram_write_enable |
wire[31:0] | An_ram_output |
wire[3:0] | dn_byteena |
Contains the microcode ROM and D0-D7, A0-A7 registers.
The memory_registers module contains:
Currently this module contains altsyncram instantiations from Altera Megafunction/LPM library.
Definition at line 2060 of file ao68000.v.
Definition at line 2093 of file ao68000.v.
02093 always @(posedge clock or negedge reset_n) begin 02094 if(reset_n == 1'b0) usp <= 32'd0; 02095 else if(An_address == 4'b0111 && An_write_enable) usp <= An_input; 02096 end
An_address [3:0] [Input] |
An_write_enable [Input] |
Dn_address [2:0] [Input] |
Dn_write_enable [Input] |
micro_data [87:0] [Output] |
An_ram_write_enable [wire] |
An_ram_output [wire[31:0]] |
dn_byteena [wire[3:0]] |
altsyncram micro_rom_inst [Module Instance] |
altsyncram dn_ram_inst [Module Instance] |
altsyncram an_ram_inst [Module Instance] |