Inputs | Outputs | Signals | Module Instances

ao68000 Module Reference

ao68000 top level module. More...

Inheritance diagram for ao68000:
bus_control registers memory_registers decoder condition alu microcode_branch

List of all members.






















Inputs

CLK_I  
 

WISHBONE Clock Input


reset_n  
 

Asynchronous Reset Input


DAT_I  [31:0]
 

WISHBONE Master Data Input


ACK_I  
 

WISHBONE Master Acknowledge Input:

  • on normal cycle: acknowledge,
  • on interrupt acknowledge cycle: external vector provided on DAT_I[7:0].

ERR_I  
 

WISHBONE Master Error Input

  • on normal cycle: bus error,
  • on interrupt acknowledge cycle: spurious interrupt.

RTY_I  
 

WISHBONE Master Retry Input

  • on normal cycle: retry bus cycle,
  • on interrupt acknowledge: use auto-vector.

ipl_i  [2:0]
 

Interrupt Priority Level Interrupt acknowledge cycle:

  • ACK_I: interrupt vector on DAT_I[7:0],
  • ERR_I: spurious interrupt,
  • RTY_I: auto-vector.

Outputs

CYC_O  
 

WISHBONE Master Cycle Output


ADR_O  [31:2]
 

WISHBONE Master Address Output


DAT_O  [31:0]
 

WISHBONE Master Data Output


SEL_O  [3:0]
 

WISHBONE Master Byte Select


STB_O  
 

WISHBONE Master Strobe Output


WE_O  
 

WISHBONE Master Write Enable Output


SGL_O  
 

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle.


BLK_O  
 

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle.


RMW_O  
 

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle.


CTI_O  [2:0]
 

WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle.


BTE_O  [1:0]
 

WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst.


fc_o  [2:0]
 

Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:

  • 1 - user data,
  • 2 - user program,
  • 5 - supervisor data : all exception vector entries except reset,
  • 6 - supervisor program : exception vector for reset,
  • 7 - cpu space: interrupt acknowledge.

reset_o  
 

External device reset. Output high when processing the RESET instruction.


blocked_o  
 

Processor blocked indicator. The processor is blocked after a double bus error.


Module Instances

bus_control::bus_control_m   Module bus_control
registers::registers_m   Module registers
memory_registers::memory_registers_m   Module memory_registers
decoder::decoder_m   Module decoder
condition::condition_m   Module condition
alu::alu_m   Module alu
microcode_branch::microcode_branch_m   Module microcode_branch

Signals

wire[15:0]  sr
wire[2:0]  size
wire[31:0]  address
wire  address_type
wire  read_modify_write_flag
wire[31:0]  data_read
wire[31:0]  data_write
wire[31:0]  pc
wire  prefetch_ir_valid
wire[79:0]  prefetch_ir
wire  do_reset
wire  do_read
wire  do_write
wire  do_interrupt
wire  do_blocked
wire  jmp_address_trap
wire  jmp_bus_trap
wire  finished
wire[7:0]  interrupt_trap
wire[2:0]  interrupt_mask
wire  rw_state
wire[2:0]  fc_state
wire[7:0]  decoder_trap
wire[31:0]  usp
wire[31:0]  Dn_output
wire[31:0]  An_output
wire[31:0]  result
wire[3:0]  An_address
wire[31:0]  An_input
wire[2:0]  Dn_address
wire[15:0]  ir
wire[8:0]  decoder_micropc
wire  alu_signal
wire  alu_mult_div_ready
wire[8:0]  load_ea
wire[8:0]  perform_ea_read
wire[8:0]  perform_ea_write
wire[8:0]  save_ea
wire  trace_flag
wire  group_0_flag
wire  stop_flag
wire[8:0]  micro_pc
wire[31:0]  operand1
wire[31:0]  operand2
wire[4:0]  movem_loop
wire[15:0]  movem_reg
wire  condition
wire[87:0]  micro_data
wire[31:0]  fault_address_state
wire[1:0]  pc_change
wire  prefetch_ir_valid_32
wire[3:0]  ea_type
wire[2:0]  ea_mod
wire[2:0]  ea_reg
wire[17:0]  decoder_alu
wire[17:0]  decoder_alu_reg

Detailed Description

ao68000 top level module.

This module contains only instantiations of sub-modules and wire declarations.

Definition at line 406 of file ao68000.v.


Member Data Documentation

CLK_I [Input]

WISHBONE Clock Input

Definition at line 408 of file ao68000.v.

ERR_I [Input]

WISHBONE Master Error Input

  • on normal cycle: bus error,
  • on interrupt acknowledge cycle: spurious interrupt.

Definition at line 420 of file ao68000.v.

RTY_I [Input]

WISHBONE Master Retry Input

  • on normal cycle: retry bus cycle,
  • on interrupt acknowledge: use auto-vector.

Definition at line 421 of file ao68000.v.

SGL_O [Output]

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle.

Definition at line 424 of file ao68000.v.

BLK_O [Output]

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle.

Definition at line 425 of file ao68000.v.

RMW_O [Output]

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle.

Definition at line 426 of file ao68000.v.

CTI_O [2:0] [Output]

WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle.

Definition at line 429 of file ao68000.v.

BTE_O [1:0] [Output]

WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst.

Definition at line 430 of file ao68000.v.

fc_o [2:0] [Output]

Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:

  • 1 - user data,
  • 2 - user program,
  • 5 - supervisor data : all exception vector entries except reset,
  • 6 - supervisor program : exception vector for reset,
  • 7 - cpu space: interrupt acknowledge.

Definition at line 433 of file ao68000.v.

ipl_i [2:0] [Input]

Interrupt Priority Level Interrupt acknowledge cycle:

  • ACK_I: interrupt vector on DAT_I[7:0],
  • ERR_I: spurious interrupt,
  • RTY_I: auto-vector.

Definition at line 441 of file ao68000.v.

reset_o [Output]

External device reset. Output high when processing the RESET instruction.

Definition at line 442 of file ao68000.v.

reset_n [Input]

Asynchronous Reset Input

Definition at line 409 of file ao68000.v.

blocked_o [Output]

Processor blocked indicator. The processor is blocked after a double bus error.

Definition at line 443 of file ao68000.v.

sr [wire[15:0]]

Definition at line 446 of file ao68000.v.

size [wire[2:0]]

Definition at line 447 of file ao68000.v.

address [wire[31:0]]

Definition at line 448 of file ao68000.v.

address_type [wire]

Definition at line 449 of file ao68000.v.

Definition at line 450 of file ao68000.v.

data_read [wire[31:0]]

Definition at line 451 of file ao68000.v.

data_write [wire[31:0]]

Definition at line 452 of file ao68000.v.

pc [wire[31:0]]

Definition at line 453 of file ao68000.v.

Definition at line 454 of file ao68000.v.

CYC_O [Output]

WISHBONE Master Cycle Output

Definition at line 411 of file ao68000.v.

prefetch_ir [wire[79:0]]

Definition at line 455 of file ao68000.v.

do_reset [wire]

Definition at line 456 of file ao68000.v.

do_read [wire]

Definition at line 457 of file ao68000.v.

do_write [wire]

Definition at line 458 of file ao68000.v.

do_interrupt [wire]

Definition at line 459 of file ao68000.v.

do_blocked [wire]

Definition at line 460 of file ao68000.v.

Definition at line 461 of file ao68000.v.

jmp_bus_trap [wire]

Definition at line 462 of file ao68000.v.

finished [wire]

Definition at line 463 of file ao68000.v.

interrupt_trap [wire[7:0]]

Definition at line 464 of file ao68000.v.

ADR_O [31:2] [Output]

WISHBONE Master Address Output

Definition at line 412 of file ao68000.v.

interrupt_mask [wire[2:0]]

Definition at line 465 of file ao68000.v.

rw_state [wire]

Definition at line 466 of file ao68000.v.

fc_state [wire[2:0]]

Definition at line 467 of file ao68000.v.

decoder_trap [wire[7:0]]

Definition at line 468 of file ao68000.v.

usp [wire[31:0]]

Definition at line 469 of file ao68000.v.

Dn_output [wire[31:0]]

Definition at line 470 of file ao68000.v.

An_output [wire[31:0]]

Definition at line 471 of file ao68000.v.

result [wire[31:0]]

Definition at line 472 of file ao68000.v.

An_address [wire[3:0]]

Definition at line 473 of file ao68000.v.

An_input [wire[31:0]]

Definition at line 474 of file ao68000.v.

DAT_O [31:0] [Output]

WISHBONE Master Data Output

Definition at line 413 of file ao68000.v.

Dn_address [wire[2:0]]

Definition at line 475 of file ao68000.v.

ir [wire[15:0]]

Definition at line 476 of file ao68000.v.

decoder_micropc [wire[8:0]]

Definition at line 477 of file ao68000.v.

alu_signal [wire]

Definition at line 478 of file ao68000.v.

Definition at line 479 of file ao68000.v.

load_ea [wire[8:0]]

Definition at line 480 of file ao68000.v.

perform_ea_read [wire[8:0]]

Definition at line 481 of file ao68000.v.

perform_ea_write [wire[8:0]]

Definition at line 482 of file ao68000.v.

save_ea [wire[8:0]]

Definition at line 483 of file ao68000.v.

trace_flag [wire]

Definition at line 484 of file ao68000.v.

DAT_I [31:0] [Input]

WISHBONE Master Data Input

Definition at line 414 of file ao68000.v.

group_0_flag [wire]

Definition at line 485 of file ao68000.v.

stop_flag [wire]

Definition at line 486 of file ao68000.v.

micro_pc [wire[8:0]]

Definition at line 487 of file ao68000.v.

operand1 [wire[31:0]]

Definition at line 488 of file ao68000.v.

operand2 [wire[31:0]]

Definition at line 489 of file ao68000.v.

movem_loop [wire[4:0]]

Definition at line 490 of file ao68000.v.

movem_reg [wire[15:0]]

Definition at line 491 of file ao68000.v.

condition [wire]

Definition at line 492 of file ao68000.v.

micro_data [wire[87:0]]

Definition at line 493 of file ao68000.v.

fault_address_state [wire[31:0]]

Definition at line 494 of file ao68000.v.

SEL_O [3:0] [Output]

WISHBONE Master Byte Select

Definition at line 415 of file ao68000.v.

pc_change [wire[1:0]]

Definition at line 495 of file ao68000.v.

Definition at line 496 of file ao68000.v.

ea_type [wire[3:0]]

Definition at line 497 of file ao68000.v.

ea_mod [wire[2:0]]

Definition at line 498 of file ao68000.v.

ea_reg [wire[2:0]]

Definition at line 499 of file ao68000.v.

decoder_alu [wire[17:0]]

Definition at line 500 of file ao68000.v.

decoder_alu_reg [wire[17:0]]

Definition at line 501 of file ao68000.v.

STB_O [Output]

WISHBONE Master Strobe Output

Definition at line 416 of file ao68000.v.

WE_O [Output]

WISHBONE Master Write Enable Output

Definition at line 417 of file ao68000.v.

ACK_I [Input]

WISHBONE Master Acknowledge Input:

  • on normal cycle: acknowledge,
  • on interrupt acknowledge cycle: external vector provided on DAT_I[7:0].

Definition at line 419 of file ao68000.v.

alu alu_m [Module Instance]

Definition at line 680 of file ao68000.v.

bus_control bus_control_m [Module Instance]

Definition at line 503 of file ao68000.v.

condition condition_m [Module Instance]

Definition at line 674 of file ao68000.v.

decoder decoder_m [Module Instance]

Definition at line 655 of file ao68000.v.

memory_registers memory_registers_m [Module Instance]

Definition at line 638 of file ao68000.v.

microcode_branch microcode_branch_m [Module Instance]

Definition at line 697 of file ao68000.v.

registers registers_m [Module Instance]

Definition at line 555 of file ao68000.v.


The documentation for this class was generated from the following file: