Microcode controlled registers. More...
Microcode controlled registers.
Most of the ao68000 IP core registers are located in this module. At every clock cycle the microcode controls what to save into these registers. Some of the more important registers include:
Definition at line 1627 of file ao68000.v.
Definition at line 1896 of file ao68000.v.
01896 always @(posedge clock or negedge reset_n) begin 01897 if(reset_n == 1'b0) address_type <= 1'b0; 01898 else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address_type <= 1'b1; 01899 else if(address_control != `ADDRESS_IDLE) address_type <= 1'b0; 01900 end
Definition at line 1902 of file ao68000.v.
01902 always @(posedge clock or negedge reset_n) begin 01903 if(reset_n == 1'b0) movem_modreg <= 6'b0; 01904 else if(movem_modreg_control == `MOVEM_MODREG_LOAD_0) movem_modreg <= 6'b0; 01905 else if(movem_modreg_control == `MOVEM_MODREG_LOAD_6b001111)movem_modreg <= 6'b001111; 01906 else if(movem_modreg_control == `MOVEM_MODREG_INCR_BY_1) movem_modreg <= movem_modreg + 6'd1; 01907 else if(movem_modreg_control == `MOVEM_MODREG_DECR_BY_1) movem_modreg <= movem_modreg - 6'd1; 01908 end
Definition at line 1910 of file ao68000.v.
01910 always @(posedge clock or negedge reset_n) begin 01911 if(reset_n == 1'b0) movem_loop <= 5'b0; 01912 else if(movem_loop_control == `MOVEM_LOOP_LOAD_0) movem_loop <= 5'b0; 01913 else if(movem_loop_control == `MOVEM_LOOP_INCR_BY_1) movem_loop <= movem_loop + 5'd1; 01914 end
Definition at line 1916 of file ao68000.v.
01916 always @(posedge clock or negedge reset_n) begin 01917 if(reset_n == 1'b0) movem_reg <= 16'b0; 01918 else if(movem_reg_control == `MOVEM_REG_FROM_OP1) movem_reg <= operand1[15:0]; 01919 else if(movem_reg_control == `MOVEM_REG_SHIFT_RIGHT) movem_reg <= { 1'b0, movem_reg[15:1] }; 01920 end
Definition at line 1922 of file ao68000.v.
01922 always @(posedge clock or negedge reset_n) begin 01923 if(reset_n == 1'b0) ir <= 16'b0; 01924 else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0) 01925 ir <= prefetch_ir[79:64]; 01926 end
Definition at line 1928 of file ao68000.v.
01928 always @(posedge clock or negedge reset_n) begin 01929 if(reset_n == 1'b0) decoder_alu_reg <= 18'b0; 01930 else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0) 01931 decoder_alu_reg <= decoder_alu; 01932 end
Definition at line 1934 of file ao68000.v.
01934 always @(posedge clock or negedge reset_n) begin 01935 if(reset_n == 1'b0) trap <= 8'd0; 01936 else if(trap_control == `TRAP_ILLEGAL_INSTR) trap <= 8'd4; 01937 else if(trap_control == `TRAP_DIV_BY_ZERO) trap <= 8'd5; 01938 else if(trap_control == `TRAP_CHK) trap <= 8'd6; 01939 else if(trap_control == `TRAP_TRAPV) trap <= 8'd7; 01940 else if(trap_control == `TRAP_PRIVIL_VIOLAT) trap <= 8'd8; 01941 else if(trap_control == `TRAP_TRACE) trap <= 8'd9; 01942 else if(trap_control == `TRAP_TRAP) trap <= { 4'b0010, ir[3:0] }; 01943 else if(trap_control == `TRAP_FROM_DECODER) trap <= decoder_trap; 01944 else if(trap_control == `TRAP_FROM_INTERRUPT) trap <= interrupt_trap; 01945 end
Definition at line 1947 of file ao68000.v.
01947 always @(posedge clock or negedge reset_n) begin 01948 if(reset_n == 1'b0) offset <= 32'd0; 01949 else if(offset_control == `OFFSET_IMM_8) offset <= { {24{prefetch_ir[71]}}, prefetch_ir[71:64] }; 01950 else if(offset_control == `OFFSET_IMM_16) offset <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] }; 01951 end
Definition at line 1953 of file ao68000.v.
01953 always @(posedge clock or negedge reset_n) begin 01954 if(reset_n == 1'b0) index <= 32'd0; 01955 else if(index_control == `INDEX_0) index <= 32'd0; 01956 else if(index_control == `INDEX_LOAD_EXTENDED) index <= 01957 (prefetch_ir[79] == 1'b0) ? 01958 ( (prefetch_ir[75] == 1'b0) ? 01959 { {16{Dn_output[15]}}, Dn_output[15:0] } : Dn_output[31:0] 01960 ) : 01961 ( (prefetch_ir[75] == 1'b0) ? 01962 { {16{An_output[15]}}, An_output[15:0] } : An_output[31:0] 01963 ); 01964 end
Definition at line 1966 of file ao68000.v.
01966 always @(posedge clock or negedge reset_n) begin 01967 if(reset_n == 1'b0) stop_flag <= 1'b0; 01968 else if(stop_flag_control == `STOP_FLAG_SET) stop_flag <= 1'b1; 01969 else if(stop_flag_control == `STOP_FLAG_CLEAR) stop_flag <= 1'b0; 01970 end
Definition at line 1747 of file ao68000.v.
01747 always @(posedge clock or negedge reset_n) begin 01748 if(reset_n == 1'b0) begin 01749 pc <= 32'd0; 01750 pc_valid <= 32'd0; 01751 end 01752 else begin 01753 if(pc_control == `PC_FROM_RESULT) pc = result; 01754 else if(pc_control == `PC_INCR_BY_2) pc = pc + 32'd2; 01755 else if(pc_control == `PC_INCR_BY_4) pc = pc + 32'd4; 01756 else if(pc_control == `PC_INCR_BY_SIZE) pc = (size[2] == 1'b0) ? pc + 32'd2 : pc + 32'd4; 01757 else if(pc_control == `PC_FROM_PREFETCH_IR) pc = prefetch_ir[47:16]; 01758 else if(pc_control == `PC_INCR_BY_2_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0) 01759 pc = pc + 32'd2; 01760 if(pc[0] == 1'b0) pc_valid <= pc; 01761 end 01762 end
Definition at line 1972 of file ao68000.v.
01972 always @(posedge clock or negedge reset_n) begin 01973 if(reset_n == 1'b0) trace_flag <= 1'b0; 01974 else if(trace_flag_control == `TRACE_FLAG_COPY_WHEN_NO_STOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0) 01975 trace_flag <= sr[15]; 01976 end
Definition at line 1978 of file ao68000.v.
01978 always @(posedge clock or negedge reset_n) begin 01979 if(reset_n == 1'b0) group_0_flag <= 1'b0; 01980 else if(group_0_flag_control == `GROUP_0_FLAG_SET) group_0_flag <= 1'b1; 01981 else if(group_0_flag_control == `GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0) 01982 group_0_flag <= 1'b0; 01983 end
Definition at line 1985 of file ao68000.v.
01985 always @(posedge clock or negedge reset_n) begin 01986 if(reset_n == 1'b0) instruction_flag <= 1'b0; 01987 else if(instruction_flag_control == `INSTRUCTION_FLAG_SET) instruction_flag <= 1'b1; 01988 else if(instruction_flag_control == `INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0) 01989 instruction_flag <= 1'b0; 01990 end
Definition at line 1992 of file ao68000.v.
01992 always @(posedge clock or negedge reset_n) begin 01993 if(reset_n == 1'b0) read_modify_write_flag <= 1'b0; 01994 else if(read_modify_write_flag_control == `READ_MODIFY_WRITE_FLAG_SET) read_modify_write_flag <= 1'b1; 01995 else if(read_modify_write_flag_control == `READ_MODIFY_WRITE_FLAG_CLEAR) read_modify_write_flag <= 1'b0; 01996 end
Definition at line 1998 of file ao68000.v.
01998 always @(posedge clock or negedge reset_n) begin 01999 if(reset_n == 1'b0) do_reset_flag <= 1'b0; 02000 else if(do_reset_flag_control == `DO_RESET_FLAG_SET) do_reset_flag <= 1'b1; 02001 else if(do_reset_flag_control == `DO_RESET_FLAG_CLEAR) do_reset_flag <= 1'b0; 02002 end
Definition at line 2004 of file ao68000.v.
02004 always @(posedge clock or negedge reset_n) begin 02005 if(reset_n == 1'b0) do_interrupt_flag <= 1'b0; 02006 else if(do_interrupt_flag_control == `DO_INTERRUPT_FLAG_SET_IF_ACTIVE) do_interrupt_flag <= (interrupt_mask != 3'b000) ? 1'b1 : 1'b0; 02007 else if(do_interrupt_flag_control == `DO_INTERRUPT_FLAG_CLEAR) do_interrupt_flag <= 1'b0; 02008 end
Definition at line 2010 of file ao68000.v.
02010 always @(posedge clock or negedge reset_n) begin 02011 if(reset_n == 1'b0) do_read_flag <= 1'b0; 02012 else if(do_read_flag_control == `DO_READ_FLAG_SET) do_read_flag <= 1'b1; 02013 else if(do_read_flag_control == `DO_READ_FLAG_CLEAR) do_read_flag <= 1'b0; 02014 end
Definition at line 2016 of file ao68000.v.
02016 always @(posedge clock or negedge reset_n) begin 02017 if(reset_n == 1'b0) do_write_flag <= 1'b0; 02018 else if(do_write_flag_control == `DO_WRITE_FLAG_SET) do_write_flag <= 1'b1; 02019 else if(do_write_flag_control == `DO_WRITE_FLAG_CLEAR) do_write_flag <= 1'b0; 02020 end
Definition at line 1774 of file ao68000.v.
01774 always @(posedge clock or negedge reset_n) begin 01775 if(reset_n == 1'b0) begin 01776 size <= 2'b00; 01777 end 01778 else if(size_control != `SIZE_IDLE) begin 01779 // BYTE 01780 size[0] <= (size_control == `SIZE_BYTE) 01781 | ((size_control == `SIZE_3) && (ir[7:6] == 2'b00)) 01782 | ((size_control == `SIZE_4) && (ir[13:12] == 2'b01)) 01783 | ((size_control == `SIZE_6) && (ir[5:3] != 3'b000)); 01784 // WORD 01785 size[1] <= (size_control == `SIZE_WORD) 01786 | ((size_control == `SIZE_1) && (ir[7:6] == 2'b00)) 01787 | ((size_control == `SIZE_1_PLUS) && (ir[7:6] == 2'b10)) 01788 | ((size_control == `SIZE_2) && (ir[6] == 1'b0)) 01789 | ((size_control == `SIZE_3) && (ir[7:6] == 2'b01)) 01790 | ((size_control == `SIZE_4) && (ir[13:12] == 2'b11)) 01791 | ((size_control == `SIZE_5) && (ir[8] == 1'b0)); 01792 // LONG 01793 size[2] <= (size_control == `SIZE_LONG) 01794 | ((size_control == `SIZE_1) && (ir[7:6] != 2'b00)) 01795 | ((size_control == `SIZE_1_PLUS) && (ir[7:6] != 2'b10)) 01796 | ((size_control == `SIZE_2) && (ir[6] == 1'b1)) 01797 | ((size_control == `SIZE_3) && (ir[7] == 1'b1)) 01798 | ((size_control == `SIZE_4) && (ir[12] == 1'b0)) 01799 | ((size_control == `SIZE_5) && (ir[8] == 1'b1)) 01800 | ((size_control == `SIZE_6) && (ir[5:3] == 3'b000)); 01801 end 01802 end
Definition at line 1804 of file ao68000.v.
01804 always @(posedge clock or negedge reset_n) begin 01805 if(reset_n == 1'b0) ea_reg <= 3'b000; 01806 else if(ea_reg_control == `EA_REG_IR_2_0) ea_reg <= ir[2:0]; 01807 else if(ea_reg_control == `EA_REG_IR_11_9) ea_reg <= ir[11:9]; 01808 else if(ea_reg_control == `EA_REG_MOVEM_REG_2_0) ea_reg <= movem_modreg[2:0]; 01809 else if(ea_reg_control == `EA_REG_3b111) ea_reg <= 3'b111; 01810 else if(ea_reg_control == `EA_REG_3b100) ea_reg <= 3'b100; 01811 end
Definition at line 1813 of file ao68000.v.
01813 always @(posedge clock or negedge reset_n) begin 01814 if(reset_n == 1'b0) ea_mod <= 3'b000; 01815 else if(ea_mod_control == `EA_MOD_IR_5_3) ea_mod <= ir[5:3]; 01816 else if(ea_mod_control == `EA_MOD_MOVEM_MOD_5_3) ea_mod <= movem_modreg[5:3]; 01817 else if(ea_mod_control == `EA_MOD_IR_8_6) ea_mod <= ir[8:6]; 01818 else if(ea_mod_control == `EA_MOD_PREDEC) ea_mod <= 3'b100; 01819 else if(ea_mod_control == `EA_MOD_3b111) ea_mod <= 3'b111; 01820 else if(ea_mod_control == `EA_MOD_DN_PREDEC) ea_mod <= (ir[3] == 1'b0) ? /* Dn **/ 3'b000 : /* -(An) **/ 3'b100; 01821 else if(ea_mod_control == `EA_MOD_DN_AN_EXG) ea_mod <= (ir[7:3] == 5'b01000 || ir[7:3] == 5'b10001) ? /* Dn **/ 3'b000 : /* An **/ 3'b001; 01822 else if(ea_mod_control == `EA_MOD_POSTINC) ea_mod <= 3'b011; 01823 else if(ea_mod_control == `EA_MOD_AN) ea_mod <= 3'b001; 01824 else if(ea_mod_control == `EA_MOD_DN) ea_mod <= 3'b000; 01825 else if(ea_mod_control == `EA_MOD_INDIRECTOFFSET) ea_mod <= 3'b101; 01826 end
Definition at line 1828 of file ao68000.v.
01828 always @(posedge clock or negedge reset_n) begin 01829 if(reset_n == 1'b0) ea_type <= `EA_TYPE_IDLE; 01830 else if(ea_type_control == `EA_TYPE_ALL) ea_type <= `EA_TYPE_ALL; 01831 else if(ea_type_control == `EA_TYPE_CONTROL_POSTINC) ea_type <= `EA_TYPE_CONTROL_POSTINC; 01832 else if(ea_type_control == `EA_TYPE_CONTROLALTER_PREDEC) ea_type <= `EA_TYPE_CONTROLALTER_PREDEC; 01833 else if(ea_type_control == `EA_TYPE_CONTROL) ea_type <= `EA_TYPE_CONTROL; 01834 else if(ea_type_control == `EA_TYPE_DATAALTER) ea_type <= `EA_TYPE_DATAALTER; 01835 else if(ea_type_control == `EA_TYPE_DN_AN) ea_type <= `EA_TYPE_DN_AN; 01836 else if(ea_type_control == `EA_TYPE_MEMORYALTER) ea_type <= `EA_TYPE_MEMORYALTER; 01837 else if(ea_type_control == `EA_TYPE_DATA) ea_type <= `EA_TYPE_DATA; 01838 end
Definition at line 1840 of file ao68000.v.
01840 always @(posedge clock or negedge reset_n) begin 01841 if(reset_n == 1'b0) operand1 <= 32'hFFFFFFFF; 01842 else if(operand1_control == `OP1_FROM_OP2) operand1 <= operand2; 01843 else if(operand1_control == `OP1_FROM_ADDRESS) operand1 <= address; 01844 else if(operand1_control == `OP1_FROM_DATA) operand1 <= 01845 (size[0] == 1'b1) ? { {24{data_read[7]}}, data_read[7:0] } : 01846 (size[1] == 1'b1) ? { {16{data_read[15]}}, data_read[15:0] } : 01847 data_read[31:0]; 01848 else if(operand1_control == `OP1_FROM_IMMEDIATE) operand1 <= 01849 (size[0] == 1'b1) ? { {24{prefetch_ir[71]}}, prefetch_ir[71:64] } : 01850 (size[1] == 1'b1) ? { {16{prefetch_ir[79]}}, prefetch_ir[79:64] } : 01851 prefetch_ir[79:48]; 01852 else if(operand1_control == `OP1_FROM_RESULT) operand1 <= result; 01853 else if(operand1_control == `OP1_MOVEQ) operand1 <= { {24{ir[7]}}, ir[7:0] }; 01854 else if(operand1_control == `OP1_FROM_PC) operand1 <= pc_valid; 01855 else if(operand1_control == `OP1_LOAD_ZEROS) operand1 <= 32'b0; 01856 else if(operand1_control == `OP1_LOAD_ONES) operand1 <= 32'hFFFFFFFF; 01857 else if(operand1_control == `OP1_FROM_SR) operand1 <= { 16'b0, sr[15], 1'b0, sr[13], 2'b0, sr[10:8], 3'b0, sr[4:0] }; 01858 else if(operand1_control == `OP1_FROM_USP) operand1 <= usp; 01859 else if(operand1_control == `OP1_FROM_AN) operand1 <= 01860 (size[1] == 1'b1) ? { {16{An_output[15]}}, An_output[15:0] } : 01861 An_output[31:0]; 01862 else if(operand1_control == `OP1_FROM_DN) operand1 <= 01863 (size[0] == 1'b1) ? { {24{Dn_output[7]}}, Dn_output[7:0] } : 01864 (size[1] == 1'b1) ? { {16{Dn_output[15]}}, Dn_output[15:0] } : 01865 Dn_output[31:0]; 01866 else if(operand1_control == `OP1_FROM_IR) operand1 <= { 16'b0, ir[15:0] }; 01867 else if(operand1_control == `OP1_FROM_FAULT_ADDRESS) operand1 <= fault_address_state; 01868 end
Definition at line 1870 of file ao68000.v.
01870 always @(posedge clock or negedge reset_n) begin 01871 if(reset_n == 1'b0) operand2 <= 32'hFFFFFFFF; 01872 else if(operand2_control == `OP2_FROM_OP1) operand2 <= operand1; 01873 else if(operand2_control == `OP2_LOAD_1) operand2 <= 32'd1; 01874 else if(operand2_control == `OP2_LOAD_COUNT) operand2 <= 01875 (ir[5] == 1'b0) ? ( (ir[11:9] == 3'b000) ? 32'b1000 : { 29'b0, ir[11:9] } ) : 01876 { 26'b0, operand2[5:0] }; 01877 else if(operand2_control == `OP2_ADDQ_SUBQ) operand2 <= (ir[11:9] == 3'b000) ? 32'b1000 : { 29'b0, ir[11:9] }; 01878 else if(operand2_control == `OP2_MOVE_OFFSET) operand2 <= (ir[7:0] == 8'b0) ? operand2[31:0] : { {24{ir[7]}}, ir[7:0] }; 01879 else if(operand2_control == `OP2_MOVE_ADDRESS_BUS_INFO) operand2 <= { 16'b0, 11'b0, rw_state, instruction_flag, fc_state}; 01880 else if(operand2_control == `OP2_DECR_BY_1) operand2 <= operand2 - 32'b1; 01881 end
Definition at line 1883 of file ao68000.v.
01883 always @(posedge clock or negedge reset_n) begin 01884 if(reset_n == 1'b0) address <= 32'b0; 01885 else if(address_control == `ADDRESS_INCR_BY_SIZE) address <= ((size[0]) && ea_reg == 3'b111) ? address + 32'd2 : address + {29'd0,size}; 01886 else if(address_control == `ADDRESS_DECR_BY_SIZE) address <= ((size[0]) && ea_reg == 3'b111) ? address - 32'd2 : address - {29'd0,size}; 01887 else if(address_control == `ADDRESS_INCR_BY_2) address <= address + 32'd2; 01888 else if(address_control == `ADDRESS_FROM_AN_OUTPUT) address <= An_output; 01889 else if(address_control == `ADDRESS_FROM_BASE_INDEX_OFFSET) address <= address + index + offset; 01890 else if(address_control == `ADDRESS_FROM_IMM_16) address <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] }; 01891 else if(address_control == `ADDRESS_FROM_IMM_32) address <= prefetch_ir[79:48]; 01892 else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address <= pc_valid + index + offset; 01893 else if(address_control == `ADDRESS_FROM_TRAP) address <= {22'b0, trap[7:0], 2'b0}; 01894 end
prefetch_ir [79:0] [Input] |
prefetch_ir_valid [Input] |
fault_address_state [31:0] [Input] |
interrupt_trap [7:0] [Input] |
interrupt_mask [2:0] [Input] |
decoder_trap [7:0] [Input] |
ea_reg_control [2:0] [Input] |
ea_mod_control [3:0] [Input] |
ea_type_control [3:0] [Input] |