clock | memory_registers | [Input] |
reset_n | memory_registers | [Input] |
An_address | memory_registers | [Input] |
An_input | memory_registers | [Input] |
An_write_enable | memory_registers | [Input] |
An_output | memory_registers | [Output] |
usp | memory_registers | [Output] |
Dn_address | memory_registers | [Input] |
Dn_input | memory_registers | [Input] |
Dn_write_enable | memory_registers | [Input] |
Dn_size | memory_registers | [Input] |
Dn_output | memory_registers | [Output] |
micro_pc | memory_registers | [Input] |
micro_data | memory_registers | [Output] |
An_ram_write_enable | memory_registers | [Signal] |
An_ram_output | memory_registers | [Signal] |
dn_byteena | memory_registers | [Signal] |
altsyncram | memory_registers | [Module Instance] |
altsyncram | memory_registers | [Module Instance] |
altsyncram | memory_registers | [Module Instance] |
ALWAYS_30clock, reset_n | memory_registers | [Always Construct] |