IO Ports

WISHBONE IO Ports

Table 1: List of WISHBONE IO ports.
Port Width Direction Description
CLK_I 1 Input

WISHBONE Clock Input

reset_n 1 Input

Asynchronous Reset Input

CYC_O 1 Output

WISHBONE Master Cycle Output

ADR_O 30 Output

WISHBONE Master Address Output

DAT_O 32 Output

WISHBONE Master Data Output

DAT_I 32 Input

WISHBONE Master Data Input

SEL_O 4 Output

WISHBONE Master Byte Select

STB_O 1 Output

WISHBONE Master Strobe Output

WE_O 1 Output

WISHBONE Master Write Enable Output

ACK_I 1 Input

WISHBONE Master Acknowledge Input:

  • on normal cycle: acknowledge,
  • on interrupt acknowledge cycle: external vector provided on DAT_I[7:0].
ERR_I 1 Input

WISHBONE Master Error Input

  • on normal cycle: bus error,
  • on interrupt acknowledge cycle: spurious interrupt.
RTY_I 1 Input

WISHBONE Master Retry Input

  • on normal cycle: retry bus cycle,
  • on interrupt acknowledge: use auto-vector.
SGL_O 1 Output

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle.

BLK_O 1 Output

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle.

RMW_O 1 Output

WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle.

CTI_O 3 Output

WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle.

BTE_O 2 Output

WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst.

fc_o 3 Output

Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:

  • 1 - user data,
  • 2 - user program,
  • 5 - supervisor data : all exception vector entries except reset,
  • 6 - supervisor program : exception vector for reset,
  • 7 - cpu space: interrupt acknowledge.

Other IO Ports

Table 2: List of Other IO ports.
Port Width Direction Description
ipl_i 3 Input

Interrupt Priority Level Interrupt acknowledge cycle:

  • ACK_I: interrupt vector on DAT_I[7:0],
  • ERR_I: spurious interrupt,
  • RTY_I: auto-vector.
reset_o 1 Output

External device reset. Output high when processing the RESET instruction.

blocked_o1 Output

Processor blocked indicator. The processor is blocked after a double bus error.