Inputs | Outputs | Signals | Module Instances | Always Constructs

memory_registers Module Reference

Contains the microcode ROM and D0-D7, A0-A7 registers. More...

Inheritance diagram for memory_registers:
ao68000

List of all members.

Always Constructs

ALWAYS_30  ( clock , reset_n )

Inputs

clock  
reset_n  
An_address  [3:0]
An_input  [31:0]
An_write_enable  
Dn_address  [2:0]
Dn_input  [31:0]
Dn_write_enable  
Dn_size  [2:0]
micro_pc  [8:0]

Outputs

An_output  [31:0]
usp  reg[31:0]
Dn_output  [31:0]
micro_data  [87:0]

Module Instances

altsyncram::an_ram_inst  
altsyncram::dn_ram_inst  
altsyncram::micro_rom_inst  

Signals

wire  An_ram_write_enable
wire[31:0]  An_ram_output
wire[3:0]  dn_byteena

Detailed Description

Contains the microcode ROM and D0-D7, A0-A7 registers.

The memory_registers module contains:

Currently this module contains altsyncram instantiations from Altera Megafunction/LPM library.

Definition at line 2060 of file ao68000.v.


Member Function Documentation

[Always Construct]
ALWAYS_30 ( clock ,
reset_n )

Definition at line 2093 of file ao68000.v.

 
02093 always @(posedge clock or negedge reset_n) begin
02094     if(reset_n == 1'b0)                                 usp <= 32'd0;
02095     else if(An_address == 4'b0111 && An_write_enable)   usp <= An_input;
02096 end

Member Data Documentation

clock [Input]

Definition at line 2061 of file ao68000.v.

reset_n [Input]

Definition at line 2062 of file ao68000.v.

An_address [3:0] [Input]

Definition at line 2065 of file ao68000.v.

An_input [31:0] [Input]

Definition at line 2066 of file ao68000.v.

An_write_enable [Input]

Definition at line 2067 of file ao68000.v.

An_output [31:0] [Output]

Definition at line 2068 of file ao68000.v.

usp reg[31:0] [Output]

Definition at line 2070 of file ao68000.v.

Dn_address [2:0] [Input]

Definition at line 2072 of file ao68000.v.

Dn_input [31:0] [Input]

Definition at line 2073 of file ao68000.v.

Dn_write_enable [Input]

Definition at line 2074 of file ao68000.v.

Dn_size [2:0] [Input]

Definition at line 2076 of file ao68000.v.

Dn_output [31:0] [Output]

Definition at line 2077 of file ao68000.v.

micro_pc [8:0] [Input]

Definition at line 2079 of file ao68000.v.

micro_data [87:0] [Output]

Definition at line 2080 of file ao68000.v.

Definition at line 2083 of file ao68000.v.

An_ram_output [wire[31:0]]

Definition at line 2085 of file ao68000.v.

dn_byteena [wire[3:0]]

Definition at line 2088 of file ao68000.v.

altsyncram micro_rom_inst [Module Instance]

Definition at line 2131 of file ao68000.v.

altsyncram dn_ram_inst [Module Instance]

Definition at line 2115 of file ao68000.v.

altsyncram an_ram_inst [Module Instance]

Definition at line 2099 of file ao68000.v.


The documentation for this class was generated from the following file: