ao68000 top level module.
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List of all members.
Inputs |
CLK_I | |
| WISHBONE Clock Input
|
reset_n | |
| Asynchronous Reset Input
|
DAT_I | [31:0] |
| WISHBONE Master Data Input
|
ACK_I | |
| WISHBONE Master Acknowledge Input:
- on normal cycle: acknowledge,
- on interrupt acknowledge cycle: external vector provided on DAT_I[7:0].
|
ERR_I | |
| WISHBONE Master Error Input
- on normal cycle: bus error,
- on interrupt acknowledge cycle: spurious interrupt.
|
RTY_I | |
| WISHBONE Master Retry Input
- on normal cycle: retry bus cycle,
- on interrupt acknowledge: use auto-vector.
|
ipl_i | [2:0] |
| Interrupt Priority Level Interrupt acknowledge cycle:
- ACK_I: interrupt vector on DAT_I[7:0],
- ERR_I: spurious interrupt,
- RTY_I: auto-vector.
|
Outputs |
CYC_O | |
| WISHBONE Master Cycle Output
|
ADR_O | [31:2] |
| WISHBONE Master Address Output
|
DAT_O | [31:0] |
| WISHBONE Master Data Output
|
SEL_O | [3:0] |
| WISHBONE Master Byte Select
|
STB_O | |
| WISHBONE Master Strobe Output
|
WE_O | |
| WISHBONE Master Write Enable Output
|
SGL_O | |
| WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle.
|
BLK_O | |
| WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle.
|
RMW_O | |
| WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle.
|
CTI_O | [2:0] |
| WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle.
|
BTE_O | [1:0] |
| WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst.
|
fc_o | [2:0] |
| Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:
- 1 - user data,
- 2 - user program,
- 5 - supervisor data : all exception vector entries except reset,
- 6 - supervisor program : exception vector for reset,
- 7 - cpu space: interrupt acknowledge.
|
reset_o | |
| External device reset. Output high when processing the RESET instruction.
|
blocked_o | |
| Processor blocked indicator. The processor is blocked after a double bus error.
|
Module Instances |
bus_control::bus_control_m | Module bus_control |
registers::registers_m | Module registers |
memory_registers::memory_registers_m | Module memory_registers |
decoder::decoder_m | Module decoder |
condition::condition_m | Module condition |
alu::alu_m | Module alu |
microcode_branch::microcode_branch_m | Module microcode_branch |
Signals |
wire[15:0] | sr |
wire[2:0] | size |
wire[31:0] | address |
wire | address_type |
wire | read_modify_write_flag |
wire[31:0] | data_read |
wire[31:0] | data_write |
wire[31:0] | pc |
wire | prefetch_ir_valid |
wire[79:0] | prefetch_ir |
wire | do_reset |
wire | do_read |
wire | do_write |
wire | do_interrupt |
wire | do_blocked |
wire | jmp_address_trap |
wire | jmp_bus_trap |
wire | finished |
wire[7:0] | interrupt_trap |
wire[2:0] | interrupt_mask |
wire | rw_state |
wire[2:0] | fc_state |
wire[7:0] | decoder_trap |
wire[31:0] | usp |
wire[31:0] | Dn_output |
wire[31:0] | An_output |
wire[31:0] | result |
wire[3:0] | An_address |
wire[31:0] | An_input |
wire[2:0] | Dn_address |
wire[15:0] | ir |
wire[8:0] | decoder_micropc |
wire | alu_signal |
wire | alu_mult_div_ready |
wire[8:0] | load_ea |
wire[8:0] | perform_ea_read |
wire[8:0] | perform_ea_write |
wire[8:0] | save_ea |
wire | trace_flag |
wire | group_0_flag |
wire | stop_flag |
wire[8:0] | micro_pc |
wire[31:0] | operand1 |
wire[31:0] | operand2 |
wire[4:0] | movem_loop |
wire[15:0] | movem_reg |
wire | condition |
wire[87:0] | micro_data |
wire[31:0] | fault_address_state |
wire[1:0] | pc_change |
wire | prefetch_ir_valid_32 |
wire[3:0] | ea_type |
wire[2:0] | ea_mod |
wire[2:0] | ea_reg |
wire[17:0] | decoder_alu |
wire[17:0] | decoder_alu_reg |
Detailed Description
ao68000 top level module.
This module contains only instantiations of sub-modules and wire declarations.
Definition at line 406 of file ao68000.v.
Member Data Documentation
WISHBONE Clock Input
Definition at line 408 of file ao68000.v.
WISHBONE Master Error Input
- on normal cycle: bus error,
- on interrupt acknowledge cycle: spurious interrupt.
Definition at line 420 of file ao68000.v.
WISHBONE Master Retry Input
- on normal cycle: retry bus cycle,
- on interrupt acknowledge: use auto-vector.
Definition at line 421 of file ao68000.v.
WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle.
Definition at line 424 of file ao68000.v.
WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle.
Definition at line 425 of file ao68000.v.
WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle.
Definition at line 426 of file ao68000.v.
WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle.
Definition at line 429 of file ao68000.v.
WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst.
Definition at line 430 of file ao68000.v.
Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:
- 1 - user data,
- 2 - user program,
- 5 - supervisor data : all exception vector entries except reset,
- 6 - supervisor program : exception vector for reset,
- 7 - cpu space: interrupt acknowledge.
Definition at line 433 of file ao68000.v.
Interrupt Priority Level Interrupt acknowledge cycle:
- ACK_I: interrupt vector on DAT_I[7:0],
- ERR_I: spurious interrupt,
- RTY_I: auto-vector.
Definition at line 441 of file ao68000.v.
External device reset. Output high when processing the RESET instruction.
Definition at line 442 of file ao68000.v.
Asynchronous Reset Input
Definition at line 409 of file ao68000.v.
Processor blocked indicator. The processor is blocked after a double bus error.
Definition at line 443 of file ao68000.v.
WISHBONE Master Cycle Output
Definition at line 411 of file ao68000.v.
WISHBONE Master Address Output
Definition at line 412 of file ao68000.v.
WISHBONE Master Data Output
Definition at line 413 of file ao68000.v.
WISHBONE Master Data Input
Definition at line 414 of file ao68000.v.
WISHBONE Master Byte Select
Definition at line 415 of file ao68000.v.
WISHBONE Master Strobe Output
Definition at line 416 of file ao68000.v.
WISHBONE Master Write Enable Output
Definition at line 417 of file ao68000.v.
WISHBONE Master Acknowledge Input:
- on normal cycle: acknowledge,
- on interrupt acknowledge cycle: external vector provided on DAT_I[7:0].
Definition at line 419 of file ao68000.v.
alu alu_m [Module Instance] |
decoder decoder_m [Module Instance] |
The documentation for this class was generated from the following file: