Initiate WISHBONE MASTER bus cycles.
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Detailed Description
Initiate WISHBONE MASTER bus cycles.
The bus_control module is the only module that has contact with signals from outside of the IP core. It is responsible for initiating WISHBONE MASTER bus cycles. The cycles can be divided into:
- memory read cycles (supervisor data, supervisor program, user data, user program)
- memory write cycles (supervisor data, user data),
- interrupt acknowledge.
Every cycle is supplemented with the following tags:
- standard WISHBONE cycle tags: SGL_O, BLK_O, RMW_O,
- register feedback WISHBONE address tags: CTI_O and BTE_O,
- ao68000 specific cycle tag: fc_o which is equivalent to MC68000 function codes.
The bus_control module is also responsible for registering interrupt inputs and initiating the interrupt acknowledge cycle in response to a microcode request. Microcode requests a interrupt acknowledge at the end of instruction processing, when the interrupt privilege level is higher than the current interrupt privilege mask, as specified in the MC68000 User's Manual.
Finally, bus_control controls also two ao68000 specific core outputs:
- blocked output, high when that the processor is blocked after encountering a double bus error. The only way to leave this block state is by reseting the ao68000 by the asynchronous reset input signal.
- reset output, high when processing the RESET instruction. Can be used to reset external devices.
Definition at line 758 of file ao68000.v.
Member Function Documentation
Definition at line 907 of file ao68000.v.
00907 always @(posedge CLK_I or negedge reset_n) begin
00908 if(reset_n == 1'b0) begin
00909 current_state <= S_INIT;
00910 interrupt_trap_o <= 8'd0;
00911 prefetch_ir_valid_o <= 1'b0;
00912 prefetch_ir_valid_32_o <= 1'b0;
00913 prefetch_ir_valid_80_o <= 1'b0;
00914
00915 jmp_address_trap_o <= 1'b0;
00916 jmp_bus_trap_o <= 1'b0;
00917
00918 CYC_O <= 1'b0;
00919 ADR_O <= 30'd0;
00920 DAT_O <= 32'd0;
00921 SEL_O <= 4'b0;
00922 STB_O <= 1'b0;
00923 WE_O <= 1'b0;
00924 SGL_O <= 1'b0;
00925 BLK_O <= 1'b0;
00926 RMW_O <= 1'b0;
00927 CTI_O <= 3'd0;
00928 fc_o <= 3'd0;
00929 reset_o <= 1'b0;
00930 blocked_o <= 1'b0;
00931 data_read_o <= 32'd0;
00932 finished_o <= 1'b0;
00933 rw_state_o <= 1'b0;
00934 fc_state_o <= 3'd0;
00935 fault_address_state_o <= 32'd0;
00936 saved_pc_change <= 2'b0;
00937 reset_counter <= 8'd0;
00938 end
00939 else begin
00940 case(current_state)
00941 S_INIT: begin
00942 finished_o <= 1'b0;
00943 jmp_address_trap_o <= 1'b0;
00944 jmp_bus_trap_o <= 1'b0;
00945 reset_o <= 1'b0;
00946 blocked_o <= 1'b0;
00947
00948 // block
00949 if(do_blocked_i == 1'b1) begin
00950 blocked_o <= 1'b1;
00951 current_state <= S_BLOCKED;
00952 end
00953 // reset
00954 else if(do_reset_i == 1'b1) begin
00955 reset_o <= 1'b1;
00956 reset_counter <= 8'd124;
00957 current_state <= S_RESET;
00958 end
00959 // read
00960 else if(do_read_i == 1'b1) begin
00961 WE_O <= 1'b0;
00962 if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;
00963 else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;
00964
00965 if(address_i[0] == 1'b1 && (size_i[0] == 1'b0)) begin // WORD or LONG WORD
00966 fault_address_state_o <= address_i;
00967 rw_state_o <= 1'b1;
00968 fc_state_o <= (supervisor_i == 1'b1) ? ((address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM) :
00969 ((address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM);
00970 interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
00971
00972 jmp_address_trap_o <= 1'b1;
00973 current_state <= S_WAIT;
00974 end
00975 else begin
00976 CYC_O <= 1'b1;
00977 ADR_O <= address_i[31:2];
00978 SEL_O <= (size_i[0] == 1'b1 && address_i[1:0] == 2'b00)? 4'b1000 :
00979 (size_i[0] == 1'b1 && address_i[1:0] == 2'b01)? 4'b0100 :
00980 (size_i[0] == 1'b1 && address_i[1:0] == 2'b10)? 4'b0010 :
00981 (size_i[0] == 1'b1 && address_i[1:0] == 2'b11)? 4'b0001 :
00982 (size_i[1] == 1'b1 && address_i[1] == 2'b0)? 4'b1100 :
00983 (size_i[0] == 1'b0 && address_i[1] == 2'b1)? 4'b0011 :
00984 4'b1111;
00985 STB_O <= 1'b1;
00986
00987 if(read_modify_write_i == 1'b1) begin
00988 SGL_O <= 1'b0;
00989 BLK_O <= 1'b0;
00990 RMW_O <= 1'b1;
00991 CTI_O <= CTI_END_OF_BURST;
00992 end
00993 else if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
00994 SGL_O <= 1'b0;
00995 BLK_O <= 1'b1;
00996 RMW_O <= 1'b0;
00997 CTI_O <= CTI_INCR_CYCLE;
00998 end
00999 else begin
01000 SGL_O <= 1'b1;
01001 BLK_O <= 1'b0;
01002 RMW_O <= 1'b0;
01003 CTI_O <= CTI_END_OF_BURST;
01004 end
01005
01006 current_state <= S_READ_1;
01007 end
01008 end
01009 // write
01010 else if(do_write_i == 1'b1) begin
01011 WE_O <= 1'b1;
01012 if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;
01013 else fc_o <= FC_USER_DATA;
01014
01015 if(address_i[0] == 1'b1 && size_i[0] == 1'b0) begin // WORD or LONG WORD
01016 fault_address_state_o <= address_i;
01017 rw_state_o <= 1'b0;
01018 fc_state_o <= (supervisor_i == 1'b1) ? FC_SUPERVISOR_DATA : FC_USER_DATA;
01019 interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
01020
01021 jmp_address_trap_o <= 1'b1;
01022 current_state <= S_WAIT;
01023 end
01024 else begin
01025 CYC_O <= 1'b1;
01026 ADR_O <= address_i[31:2];
01027 STB_O <= 1'b1;
01028
01029 if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
01030 DAT_O <= { 16'b0, data_write_i[31:16] };
01031 SEL_O <= 4'b0011;
01032 end
01033 else if(address_i[1:0] == 2'b00 && size_i[2] == 1'b1) begin
01034 DAT_O <= data_write_i[31:0];
01035 SEL_O <= 4'b1111;
01036 end
01037 else if(address_i[1:0] == 2'b10 && size_i[1] == 1'b1) begin
01038 DAT_O <= { 16'b0, data_write_i[15:0] };
01039 SEL_O <= 4'b0011;
01040 end
01041 else if(address_i[1:0] == 2'b00 && size_i[1] == 1'b1) begin
01042 DAT_O <= { data_write_i[15:0], 16'b0 };
01043 SEL_O <= 4'b1100;
01044 end
01045 else if(address_i[1:0] == 2'b11 && size_i[0] == 1'b1) begin
01046 DAT_O <= { 24'b0, data_write_i[7:0] };
01047 SEL_O <= 4'b0001;
01048 end
01049 else if(address_i[1:0] == 2'b10 && size_i[0] == 1'b1) begin
01050 DAT_O <= { 16'b0, data_write_i[7:0], 8'b0 };
01051 SEL_O <= 4'b0010;
01052 end
01053 else if(address_i[1:0] == 2'b01 && size_i[0] == 1'b1) begin
01054 DAT_O <= { 8'b0, data_write_i[7:0], 16'b0 };
01055 SEL_O <= 4'b0100;
01056 end
01057 else if(address_i[1:0] == 2'b00 && size_i[0] == 1'b1) begin
01058 DAT_O <= { data_write_i[7:0], 24'b0 };
01059 SEL_O <= 4'b1000;
01060 end
01061
01062 if(read_modify_write_i == 1'b1) begin
01063 SGL_O <= 1'b0;
01064 BLK_O <= 1'b0;
01065 RMW_O <= 1'b1;
01066 CTI_O <= CTI_END_OF_BURST;
01067 end
01068 else if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
01069 SGL_O <= 1'b0;
01070 BLK_O <= 1'b1;
01071 RMW_O <= 1'b0;
01072 CTI_O <= CTI_INCR_CYCLE;
01073 end
01074 else begin
01075 SGL_O <= 1'b1;
01076 BLK_O <= 1'b0;
01077 RMW_O <= 1'b0;
01078 CTI_O <= CTI_END_OF_BURST;
01079 end
01080
01081 current_state <= S_WRITE_1;
01082 end
01083 end
01084 // pc
01085 else if(prefetch_ir_valid_o == 1'b0 || pc_change_i != 2'b00) begin
01086
01087 if(prefetch_ir_valid_o == 1'b0 || pc_change_i == 2'b10 || pc_change_i == 2'b11) begin
01088 // load 4 words: [79:16] in 2,3 cycles
01089 prefetch_ir_valid_32_o <= 1'b0;
01090 prefetch_ir_valid_o <= 1'b0;
01091 prefetch_ir_valid_80_o <= 1'b0;
01092
01093 current_state <= S_PC_0;
01094 end
01095 else if(prefetch_ir_valid_80_o == 1'b0 && pc_change_i == 2'b01) begin
01096 // load 2 words: [31:0] in 1 cycle
01097 prefetch_ir_valid_32_o <= 1'b1;
01098 prefetch_ir_valid_o <= 1'b0;
01099 prefetch_ir_valid_80_o <= 1'b0;
01100
01101 prefetch_ir_o <= { prefetch_ir_o[63:0], 16'b0 };
01102 current_state <= S_PC_0;
01103 end
01104 else begin
01105 // do not load any words
01106 prefetch_ir_valid_32_o <= 1'b1;
01107 prefetch_ir_valid_o <= 1'b1;
01108 prefetch_ir_valid_80_o <= 1'b0;
01109
01110 prefetch_ir_o <= { prefetch_ir_o[63:0], 16'b0 };
01111 end
01112
01113
01114 end
01115 // interrupt
01116 else if(do_interrupt_i == 1'b1) begin
01117 CYC_O <= 1'b1;
01118 ADR_O <= { 27'b111_1111_1111_1111_1111_1111_1111, last_interrupt_mask };
01119 SEL_O <= 4'b1111;
01120 STB_O <= 1'b1;
01121 WE_O <= 1'b0;
01122
01123 SGL_O <= 1'b1;
01124 BLK_O <= 1'b0;
01125 RMW_O <= 1'b0;
01126 CTI_O <= CTI_END_OF_BURST;
01127
01128 fc_o <= FC_CPU_SPACE;
01129
01130 current_state <= S_INT_1;
01131 end
01132 end
01133
01134 S_RESET: begin
01135 reset_counter <= reset_counter - 8'd1;
01136
01137 if(reset_counter == 8'd0) begin
01138 finished_o <= 1'b1;
01139 current_state <= S_WAIT;
01140 end
01141 end
01142
01143 S_BLOCKED: begin
01144 end
01145
01146 S_INT_1: begin
01147 if(ACK_I == 1'b1) begin
01148 CYC_O <= 1'b0;
01149 STB_O <= 1'b0;
01150
01151 interrupt_trap_o <= DAT_I[7:0];
01152
01153 finished_o <= 1'b1;
01154 current_state <= S_WAIT;
01155 end
01156 else if(RTY_I == 1'b1) begin
01157 CYC_O <= 1'b0;
01158 STB_O <= 1'b0;
01159
01160 interrupt_trap_o <= 8'd24 + { 5'b0, interrupt_mask_o };
01161
01162 finished_o <= 1'b1;
01163 current_state <= S_WAIT;
01164 end
01165 else if(ERR_I == 1'b1) begin
01166 CYC_O <= 1'b0;
01167 STB_O <= 1'b0;
01168
01169 interrupt_trap_o <= 8'd24; // spurious interrupt
01170
01171 finished_o <= 1'b1;
01172 current_state <= S_WAIT;
01173 end
01174 end
01175
01176 S_PC_0: begin
01177 WE_O <= 1'b0;
01178 if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
01179 else fc_o <= FC_USER_PROGRAM;
01180
01181 if(pc_i[0] == 1'b1) begin
01182 prefetch_ir_valid_32_o <= 1'b1;
01183 prefetch_ir_valid_o <= 1'b1;
01184 prefetch_ir_valid_80_o <= 1'b1;
01185
01186 fault_address_state_o <= pc_i;
01187 rw_state_o <= 1'b1;
01188 fc_state_o <= (supervisor_i == 1'b1) ? FC_SUPERVISOR_PROGRAM : FC_USER_PROGRAM;
01189 interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
01190
01191 jmp_address_trap_o <= 1'b1;
01192 current_state <= S_WAIT;
01193 end
01194 else begin
01195 CYC_O <= 1'b1;
01196
01197 if(prefetch_ir_valid_32_o == 1'b0) ADR_O <= pc_i[31:2];
01198 else ADR_O <= pc_i_plus_6[31:2];
01199
01200 SEL_O <= (pc_i[1:0] == 2'b10)? 4'b0011 :
01201 4'b1111;
01202 STB_O <= 1'b1;
01203
01204 if(prefetch_ir_valid_32_o == 1'b0) begin
01205 SGL_O <= 1'b0;
01206 BLK_O <= 1'b1;
01207 RMW_O <= 1'b0;
01208 CTI_O <= CTI_INCR_CYCLE;
01209 end
01210 else begin
01211 SGL_O <= 1'b1;
01212 BLK_O <= 1'b0;
01213 RMW_O <= 1'b0;
01214 CTI_O <= CTI_END_OF_BURST;
01215 end
01216
01217 saved_pc_change <= pc_change_i;
01218 prefetch_ir_valid_32_o <= 1'b0;
01219
01220 current_state <= S_PC_1;
01221 end
01222 end
01223
01224 S_PC_1: begin
01225 if(pc_change_i != 2'b00) saved_pc_change <= pc_change_i;
01226
01227 if(ACK_I == 1'b1) begin
01228 if(CTI_O == CTI_INCR_CYCLE) begin
01229 //CYC_O <= 1'b1;
01230 ADR_O <= pc_i_plus_4[31:2];
01231 SEL_O <= 4'b1111;
01232 //STB_O <= 1'b1;
01233 //WE_O <= 1'b0;
01234
01235 if(pc_i[1:0] == 2'b10) begin
01236 SGL_O <= 1'b0;
01237 BLK_O <= 1'b1;
01238 RMW_O <= 1'b0;
01239 CTI_O <= CTI_INCR_CYCLE;
01240 end
01241 else begin
01242 SGL_O <= 1'b0;
01243 BLK_O <= 1'b1;
01244 RMW_O <= 1'b0;
01245 CTI_O <= CTI_END_OF_BURST;
01246 end
01247
01248 //if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
01249 //else fc_o <= FC_USER_PROGRAM;
01250
01251 if(pc_i[1:0] == 2'b10) prefetch_ir_o <= { DAT_I[15:0], 64'b0 };
01252 else prefetch_ir_o <= { DAT_I[31:0], 48'b0 };
01253
01254 current_state <= S_PC_3;
01255 end
01256 else begin
01257 CYC_O <= 1'b0;
01258 STB_O <= 1'b0;
01259
01260 if(saved_pc_change == 2'b10 || saved_pc_change == 2'b11 || pc_change_i == 2'b10 || pc_change_i == 2'b11) begin
01261 // load 4 words: [79:16] in 2,3 cycles
01262 prefetch_ir_valid_32_o <= 1'b0;
01263 prefetch_ir_valid_o <= 1'b0;
01264 prefetch_ir_valid_80_o <= 1'b0;
01265
01266 current_state <= S_PC_0;
01267 end
01268 else if(saved_pc_change == 2'b01 || pc_change_i == 2'b01) begin
01269 // do not load any words
01270 prefetch_ir_valid_32_o <= 1'b1;
01271 prefetch_ir_valid_o <= 1'b1;
01272 prefetch_ir_valid_80_o <= 1'b0;
01273
01274 prefetch_ir_o <= { prefetch_ir_o[63:32], DAT_I[31:0], 16'b0 };
01275 current_state <= S_INIT;
01276 end
01277 else begin
01278 prefetch_ir_valid_32_o <= 1'b1;
01279 prefetch_ir_valid_o <= 1'b1;
01280 prefetch_ir_valid_80_o <= 1'b1;
01281
01282 prefetch_ir_o <= { prefetch_ir_o[79:32], DAT_I[31:0] };
01283 current_state <= S_INIT;
01284 end
01285 end
01286 end
01287 else if(RTY_I == 1'b1) begin
01288 CYC_O <= 1'b0;
01289 STB_O <= 1'b0;
01290
01291 current_state <= S_PC_2;
01292 end
01293 else if(ERR_I == 1'b1) begin
01294 CYC_O <= 1'b0;
01295 STB_O <= 1'b0;
01296
01297 fault_address_state_o <= { ADR_O, 2'b00 };
01298 rw_state_o <= ~WE_O;
01299 fc_state_o <= fc_o;
01300 interrupt_trap_o <= VECTOR_BUS_TRAP;
01301
01302 jmp_bus_trap_o <= 1'b1;
01303 current_state <= S_WAIT;
01304 end
01305 end
01306 S_PC_2: begin
01307 CYC_O <= 1'b1;
01308 STB_O <= 1'b1;
01309
01310 current_state <= S_PC_1;
01311 end
01312 S_PC_3: begin
01313 if(ACK_I == 1'b1) begin
01314 if(pc_i[1:0] == 2'b10) begin
01315 //CYC_O <= 1'b1;
01316 ADR_O <= pc_i_plus_6[31:2];
01317 SEL_O <= 4'b1111;
01318 //STB_O <= 1'b1;
01319 //WE_O <= 1'b0;
01320
01321 SGL_O <= 1'b0;
01322 BLK_O <= 1'b1;
01323 RMW_O <= 1'b0;
01324 CTI_O <= CTI_END_OF_BURST;
01325
01326 //if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
01327 //else fc_o <= FC_USER_PROGRAM;
01328
01329 prefetch_ir_o <= { prefetch_ir_o[79:64], DAT_I[31:0], 32'b0 };
01330
01331 current_state <= S_PC_5;
01332 end
01333 else begin
01334 CYC_O <= 1'b0;
01335 STB_O <= 1'b0;
01336
01337 prefetch_ir_o <= { prefetch_ir_o[79:48], DAT_I[31:0], 16'b0 };
01338
01339 prefetch_ir_valid_32_o <= 1'b1;
01340 prefetch_ir_valid_o <= 1'b1;
01341 prefetch_ir_valid_80_o <= 1'b0;
01342 current_state <= S_INIT;
01343 end
01344 end
01345 else if(RTY_I == 1'b1) begin
01346 CYC_O <= 1'b0;
01347 STB_O <= 1'b0;
01348
01349 current_state <= S_PC_4;
01350 end
01351 else if(ERR_I == 1'b1) begin
01352 CYC_O <= 1'b0;
01353 STB_O <= 1'b0;
01354
01355 fault_address_state_o <= { ADR_O, 2'b00 };
01356 rw_state_o <= ~WE_O;
01357 fc_state_o <= fc_o;
01358 interrupt_trap_o <= VECTOR_BUS_TRAP;
01359
01360 jmp_bus_trap_o <= 1'b1;
01361 current_state <= S_WAIT;
01362 end
01363 end
01364 S_PC_4: begin
01365 CYC_O <= 1'b1;
01366 STB_O <= 1'b1;
01367
01368 current_state <= S_PC_3;
01369 end
01370 S_PC_5: begin
01371 if(ACK_I == 1'b1) begin
01372 CYC_O <= 1'b0;
01373 STB_O <= 1'b0;
01374
01375 prefetch_ir_o <= { prefetch_ir_o[79:32], DAT_I[31:0] };
01376
01377 prefetch_ir_valid_32_o <= 1'b1;
01378 prefetch_ir_valid_o <= 1'b1;
01379 prefetch_ir_valid_80_o <= 1'b1;
01380 current_state <= S_INIT;
01381 end
01382 else if(RTY_I == 1'b1) begin
01383 CYC_O <= 1'b0;
01384 STB_O <= 1'b0;
01385
01386 current_state <= S_PC_6;
01387 end
01388 else if(ERR_I == 1'b1) begin
01389 CYC_O <= 1'b0;
01390 STB_O <= 1'b0;
01391
01392 fault_address_state_o <= { ADR_O, 2'b00 };
01393 rw_state_o <= ~WE_O;
01394 fc_state_o <= fc_o;
01395 interrupt_trap_o <= VECTOR_BUS_TRAP;
01396
01397 jmp_bus_trap_o <= 1'b1;
01398 current_state <= S_WAIT;
01399 end
01400 end
01401 S_PC_6: begin
01402 CYC_O <= 1'b1;
01403 STB_O <= 1'b1;
01404
01405 current_state <= S_PC_5;
01406 end
01407
01408 //*******************
01409 S_READ_1: begin
01410 if(ACK_I == 1'b1) begin
01411 if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
01412 //CYC_O <= 1'b1;
01413 ADR_O <= address_i_plus_4[31:2];
01414 SEL_O <= 4'b1100;
01415 //STB_O <= 1'b1;
01416 //WE_O <= 1'b0;
01417
01418 //SGL_O <= 1'b0;
01419 //BLK_O <= 1'b1;
01420 //RMW_O <= 1'b0;
01421 CTI_O <= CTI_END_OF_BURST;
01422
01423 //if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;
01424 //else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;
01425
01426 data_read_o <= { DAT_I[15:0], 16'b0 };
01427
01428 current_state <= S_READ_2;
01429 end
01430 else begin
01431 if(read_modify_write_i == 1'b1) begin
01432 CYC_O <= 1'b1;
01433 STB_O <= 1'b0;
01434 end
01435 else begin
01436 CYC_O <= 1'b0;
01437 STB_O <= 1'b0;
01438 end
01439
01440 if(address_i[1:0] == 2'b00 && size_i[2] == 1'b1) data_read_o <= DAT_I[31:0];
01441 else if(address_i[1:0] == 2'b10 && size_i[1] == 1'b1) data_read_o <= { {16{DAT_I[15]}}, DAT_I[15:0] };
01442 else if(address_i[1:0] == 2'b00 && size_i[1] == 1'b1) data_read_o <= { {16{DAT_I[31]}}, DAT_I[31:16] };
01443 else if(address_i[1:0] == 2'b11 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[7]}}, DAT_I[7:0] };
01444 else if(address_i[1:0] == 2'b10 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[15]}}, DAT_I[15:8] };
01445 else if(address_i[1:0] == 2'b01 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[23]}}, DAT_I[23:16] };
01446 else if(address_i[1:0] == 2'b00 && size_i[0] == 1'b1) data_read_o <= { {24{DAT_I[31]}}, DAT_I[31:24] };
01447
01448 finished_o <= 1'b1;
01449 current_state <= S_WAIT;
01450 end
01451 end
01452 else if(RTY_I == 1'b1) begin
01453 CYC_O <= 1'b0;
01454 STB_O <= 1'b0;
01455
01456 current_state <= S_INIT;
01457 end
01458 else if(ERR_I == 1'b1) begin
01459 CYC_O <= 1'b0;
01460 STB_O <= 1'b0;
01461
01462 fault_address_state_o <= { ADR_O, 2'b00 };
01463 rw_state_o <= ~WE_O;
01464 fc_state_o <= fc_o;
01465 interrupt_trap_o <= VECTOR_BUS_TRAP;
01466
01467 jmp_bus_trap_o <= 1'b1;
01468 current_state <= S_WAIT;
01469 end
01470 end
01471 S_READ_2: begin
01472 if(ACK_I == 1'b1) begin
01473 CYC_O <= 1'b0;
01474 STB_O <= 1'b0;
01475
01476 data_read_o <= { data_read_o[31:16], DAT_I[31:16] };
01477
01478 finished_o <= 1'b1;
01479 current_state <= S_WAIT;
01480
01481 end
01482 else if(RTY_I == 1'b1) begin
01483 CYC_O <= 1'b0;
01484 STB_O <= 1'b0;
01485
01486 current_state <= S_READ_3;
01487 end
01488 else if(ERR_I == 1'b1) begin
01489 CYC_O <= 1'b0;
01490 STB_O <= 1'b0;
01491
01492 fault_address_state_o <= { ADR_O, 2'b00 };
01493 rw_state_o <= ~WE_O;
01494 fc_state_o <= fc_o;
01495 interrupt_trap_o <= VECTOR_BUS_TRAP;
01496
01497 jmp_bus_trap_o <= 1'b1;
01498 current_state <= S_WAIT;
01499 end
01500
01501 end
01502 S_READ_3: begin
01503 CYC_O <= 1'b1;
01504 STB_O <= 1'b1;
01505
01506 current_state <= S_READ_2;
01507 end
01508
01509
01510 S_WAIT: begin
01511 jmp_address_trap_o <= 1'b0;
01512 jmp_bus_trap_o <= 1'b0;
01513
01514 if(do_read_i == 1'b0 && do_write_i == 1'b0 && do_interrupt_i == 1'b0 && do_reset_i == 1'b0) begin
01515 finished_o <= 1'b0;
01516 current_state <= S_INIT;
01517 end
01518 end
01519
01520 //**********************
01521 S_WRITE_1: begin
01522 if(ACK_I == 1'b1) begin
01523 if(address_i[1:0] == 2'b10 && size_i[2] == 1'b1) begin
01524 //CYC_O <= 1'b1;
01525 ADR_O <= address_i_plus_4[31:2];
01526 //STB_O <= 1'b1;
01527 //WE_O <= 1'b1;
01528
01529 DAT_O <= { data_write_i[15:0], 16'b0 };
01530 SEL_O <= 4'b1100;
01531
01532 //SGL_O <= 1'b0;
01533 //BLK_O <= 1'b1;
01534 //RMW_O <= 1'b0;
01535 CTI_O <= CTI_END_OF_BURST;
01536
01537 //if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;
01538 //else fc_o <= FC_USER_DATA;
01539
01540 current_state <= S_WRITE_2;
01541 end
01542 else begin
01543 CYC_O <= 1'b0;
01544 STB_O <= 1'b0;
01545
01546 finished_o <= 1'b1;
01547 current_state <= S_WAIT;
01548 end
01549 end
01550 else if(RTY_I == 1'b1) begin
01551 CYC_O <= 1'b0;
01552 STB_O <= 1'b0;
01553
01554 current_state <= S_INIT;
01555 end
01556 else if(ERR_I == 1'b1) begin
01557 CYC_O <= 1'b0;
01558 STB_O <= 1'b0;
01559
01560 fault_address_state_o <= { ADR_O, 2'b00 };
01561 rw_state_o <= ~WE_O;
01562 fc_state_o <= fc_o;
01563 interrupt_trap_o <= VECTOR_BUS_TRAP;
01564
01565 jmp_bus_trap_o <= 1'b1;
01566 current_state <= S_WAIT;
01567 end
01568
01569 end
01570 S_WRITE_2: begin
01571 if(ACK_I == 1'b1) begin
01572 CYC_O <= 1'b0;
01573 STB_O <= 1'b0;
01574
01575 finished_o <= 1'b1;
01576 current_state <= S_WAIT;
01577
01578 end
01579 else if(RTY_I == 1'b1) begin
01580 CYC_O <= 1'b0;
01581 STB_O <= 1'b0;
01582
01583 current_state <= S_WRITE_3;
01584 end
01585 else if(ERR_I == 1'b1) begin
01586 CYC_O <= 1'b0;
01587 STB_O <= 1'b0;
01588
01589 fault_address_state_o <= { ADR_O, 2'b00 };
01590 rw_state_o <= ~WE_O;
01591 fc_state_o <= fc_o;
01592 interrupt_trap_o <= VECTOR_BUS_TRAP;
01593
01594 jmp_bus_trap_o <= 1'b1;
01595 current_state <= S_WAIT;
01596 end
01597
01598 end
01599 S_WRITE_3: begin
01600 CYC_O <= 1'b1;
01601 STB_O <= 1'b1;
01602
01603 current_state <= S_WRITE_2;
01604 end
01605
01606 endcase
01607 end
01608 end
Member Data Documentation
The documentation for this class was generated from the following file: